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ds04-21341-2e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer mb15f02 n description the fujitsu mb15f02 is a serial input phase locked loop (pll) frequency synthesizer with a 2.0 ghz and a 500 mhz prescalers. a 64/65 or a 128/129 for the 1.2 ghz prescaler, and a 16/17 or a 32/33 for 500 mhz prescaler can be selected that enables pulse swallow operation. the latest bicmos process technology is used, resuitantly a supply current is limited as low as 6.0 ma typ. at a supply voltage of 3.0 v. furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. as a result of this, mb15f02 is ideally suitable for digital mobile communications, such as gsm (global system for mobile communications). n features high frequency operation rf synthesizer : 1.2 ghz max. if synthesizer : 500 mhz max. low power supply voltage: v cc = 2.7 to 3.6v very low power supply current : i cc = 6.0 ma typ. (v cc = 3 v) power saving function : i ps1 = i ps2 = 0.1 m a typ. serial input 14?it programmable reference divider: r = 5 to 16,383 serial input 18?it programmable divider consisting of: - binary 7?it swallow counter: 0 to 127 - binary 11?it programmable counter: 5 to 2,047 on?hip high performance charge pump circuit and phase comparator, achieving high?peed lock?p and low phase noise wide operating temperature: ta = - 40 to 85 c plastic 16-pin ssop package (fpt-16p-m05) and 16-pin bcc package (lcc-16p-m03) n packages 16-pin, plastic ssop (fpt-16p-m05) (lcc-16p-m03) 16-pin, plastic bcc
2 mb15f02 n pin assignments top 1 2 3 4 5 6 16 15 14 13 12 11 7 8 10 9 view gnd rf gnd if ? if oscin vcc if ps if do if ld/fout clock data le ? rf vcc rf x? rf ps rf do rf ssop-16 pin bcc-16 pin 14 13 12 11 10 9 data le fin rf v ccrf xfin rf ps rf 1 2 3 4 5 6 oscin fin if v ccif ld/fout ps if gnd if 78 16 15 do if do rf gnd rf clock top view (fpt-16p-m05) (lcc-16p-m03)
3 mb15f02 n pin descriptions pin no. pin name i/o descriptions ssop bcc 1 16 gnd rf ground for rf?ll section. 2 1 oscin i the programmable reference divider input. tcxo should be connected with a coupling capacitor. 3 2 gnd if ground for the if-pll section. 4 3 fin if i prescaler input pin for the if-pll. the connection with vco should be ac coupling. 5 4 vcc if power supply voltage input pin for the if-pll section. 6 5 ld/fout o lock detect signal output (ld) / phase comparator monitoring output (fout) the output signal is selected by a lds bit in a serial data. lds bit = ? ; outputs fout signal lds bit = ? ; outputs ld signal 76ps if i power saving mode control for the if-pll section. this pin must be set at ? power-on. (open is prohibited.) ps if = ??; normal mode ps if = ??; power saving mode 87do if o charge pump output for the if-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 98do rf o charge pump output for the rf-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 10 9 ps rf i power saving mode control for the rf-pll section. this pin must be set at ? power-on. (open is prohibited.) ps rf = ? ; normal mode ps rf = ? ; power saving mode 11 10 xfin rf i prescaler complimentary input for the rf-pll section. this pin should be grounded via a capacitor. 12 11 vcc rf power supply voltage input pin for the rf-pll section, the shift register and the oscillator input buffer. 13 12 fin rf i prescaler input pin for the rf-pll. the connection with vco should be ac coupling. 14 13 le i load enable signal input (with the schmitt trigger circuit.) when le is ?? data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 15 14 data i serial data input (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (if-ref counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 16 15 clock i clock input for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a riging edge of the clock.
4 mb15f02 n block diagram ps rf 2 4 14 schmitt circuit 15 schmitt circuit 16 schmitt circuit c n 1 23-bit shift register latch selector 1 v cc rf 12 gnd rf ? if oscin le data clock 5 vcc if prescaler (if?ll) 16/17,32/33 intermittent mode control (if?ll) c n 2 3-bit latch lds sw if fc if binary 7-bit swallow counter (if?ll) binary 11-bit programmable counter (if?ll) phase comp. (if?ll) charge pump (if?ll) super charger 7 ps if 7-bit latch 11-bit latch 2-bit latch 14-bit latch binary 14?it pro- grammable ref. counter(if?ll) 10 13 ? rf prescaler (rf?ll) 64/65, 128/129 3-bit latch lds sw rf fc rf binary 7-bit swallow counter (rf?ll) binary 11-bit programmable counter (rf?ll) charge pump (rf?ll) super charger 7-bit latch 11-bit latch t1 t2 2-bit latch 14-bit latch binary 14-bit pro- grammable ref. counter (rf?ll) t1 t2 or lock det. (if?ll) lock det. (rf?ll) selector ld fr if fr rf fp if fp rf 9 do rf 8 do if and 6 ld/fout 11 x? rf 3 gnd if fr if fr rf ldif fp rf fp if intermittent mode control (rf?ll) phase comp. (rf?ll) ldrf note: ssop-16 pin
5 mb15f02 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always yse semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with repect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol rating unit remark power supply voltage v cc ?.5 to +4.0 v input voltage v i ?.5 to v cc +0.5 v output voltage v o ?.5 to v cc +0.5 v storage temperature t stg ?5 to +125 c parameter symbol value unit note min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v input voltage v i gnd v cc v operating temperature ta ?0 +85 c
6 mb15f02 n electrical characteristics (v cc = 2.7 to 3.6 v, ta = ?0 to +85 c) *1: conditions ; vcc if = 3.0 v, ta = 25 c, in locking state. *2: conditions; vcc rf = 3.0 v, ta = 25 c, in locking state. *3: conditions ; vcc = 3.0 v, fosc = 12.8 mhz (? db), ta = 25 c *4: ac coupling. the minimum frequency is speci?d with a connecting coupling capacitor of 1000 pf. *5: the symbol means direction of current ?w. parameter symbol condition value unit min. typ. max. power supply current i ccif *1 ? if = 500 mhz, fosc = 12 mhz 2.5 ma i ccrf *2 ? rf = 1200 mhz, fosc = 12 mhz 3.5 power saving current ips if vcc if current at ps if =? 0.1 *3 10 m a ips rf vcc rf current at ps if/rf =? 0.1 *3 10 operating frequency ? if fin if *4 if?ll 50 500 mhz ? rf fin rf *4 rf?ll 100 1200 oscin f osc 340 input sensitivity ? if vfin if if?ll, 50 w load system (refer to the test circuit) ?0 +2 dbm ? rf vfin rf rf?ll, 50 w load system (refer to the test circuit) ?0 +2 dbm oscin v osc 0.5 v cc vp-p input voltage data, clock, le v ih schmitt trigger input v cc 0.7+0.4 v v il schmitt trigger input v cc 0.3?.4 ps if , ps rf v ih v cc 0.7 v v il v cc 0.3 input current data, clock, le, ps if , ps rf i ih *5 ?.0 +1.0 m a i il *5 ?.0 +1.0 oscin i ih 0 +100 m a i il *5 ?00 0 output voltage ld/fout v oh vcc = 3.0 v, i oh = ? ma v cc ?.4 v v ol vcc = 3.0 v, i ol = 1 ma 0.4 do if , do rf v doh vcc = 3.0 v, i oh = ? ma v cc ?.4 v v dol vcc = 3.0 v, i ol = 1 ma 0.4 high impedance cutoff current do if , do rf i off vcc = 3.0 v v off = gnd to vcc 1.1 m a output current ld/fout i oh *5 vcc = 3.0 v ?.0 ma i ol vcc = 3.0 v 1.0 do if , do rf i doh *5 vcc = 3.0 v, v doh = 2.0 v, ta = 25 c ?1 6 ma i dol vcc = 3.0 v, v dol = 1.0 v, ta = 25 c 815
7 mb15f02 n functional descriptions the divide ratio can be calculated using the following equation: f vco = {(m x n) + a} x f osc ? r (a < n) f vco : output frequency of external voltage controlled ocillator (vco) m: preset divide ratio of dual modulus prescaler (16 or 32 for if-pll, 64 or 128 for rf-pll) n: preset divide ratio of binary 11-bit programmable counter (5 to 2,047) a: preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : reference oscillation frequency r: preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf?ll sections, programmable reference dividers of if/rf pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. when load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table1. control bit shift register con?uration control bit destination of serial data cn1 cn2 ll the programmable reference counter for the if-pll. hl the programmable reference counter for the rf-pll. lh the programmable counter and the swallow counter for the if-pll hh the programmable counter and the swallow counter for the rf-pll programmable reference counter c n 1 1 2 t 1 3 r 1 4 r 2 5 r 3 6 r 4 7 r 5 8 r 6 9 r 7 10 r 8 11 r 9 12 r 10 13 r 11 14 r 12 15 r 13 16 r 14 17 ls ms data c n 2 t 2 18 cnt1, 2 : control bit [table. 1] r1 to r14 : divide ratio setting bits for the programmable reference counter (5 to 16,383) [table. 2] t1, 2 : test purpose bit [table. 3] note: start data input with msb ?st.
8 mb15f02 table2. binary 14-bit programmable reference counter data setting note: divide ratio less than 5 is prohibited. table.3 test purpose bit setting divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 5 00000000000101 6 00000000000110 16383 1 1111111111111 t 1 t 2 ld/fout pin state l l outputs fr if. h l outputs fr rf. l h outputs fp if. h h outputs fp rf. programmable counter c n 1 1 2 l d 3 f c 4 a 1 5 a 2 6 a 3 7 a 4 8 a 5 9 a 6 10 a 7 11 n 1 12 n 2 13 n 3 14 n 4 15 n 5 16 n 6 17 ls ms data c n 2 s w 18 cnt1, 2 : control bit [table. 1] n1 to n14 : divide ratio setting bits for the programmable counter (5 to 2,047) [table. 4] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table. 5] sw : divide ratio setting bit for the prescaler [table. 6] (16/17 or 32/33 for the if-pll, 64/65 or 128/129 for the rf-pll) fc : phase control bit for the phase detector [table. 7] lds : ld/fout signal select bit [table. 8] note: start data input with msb ?st. n 7 n 8 19 n 9 20 n 10 21 n 11 22 23 s
9 mb15f02 table.4 binary 11-bit programmable counter data setting note: divide ratio less than 5 is prohibited. table.5 binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table. 6 prescaler data setting divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 5 00000000101 6 00000000110 2047 1 1 1 1 1 1 1 1 1 1 1 divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw = ? sw = ? prescaler divide ratio if-pll 16/17 32/33 rf-pll 64/65 128/129
10 mb15f02 table. 7 phase comparator phase switching data setting note: z = high?mpedance depending upon the vco and lpf polarity, fc bit should be set. table. 8 ld/fout output select data setting serial data input timing fc if/rf = h fc if/rf = l do if/rf fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) lds ld/fout output signal h fout (fr if/rf , fp if/rf ) signals l ld signal vco input voltage vco output frequency (1) (2) msb lsb data clock le t1 t2 t4 t5 t3 on rising edge of the clock, one bit of the data is transferred into the shift register. t6 t7 parameter unit max. typ. min. t1 t2 t3 t4 ns ns ns ns 20 20 30 30 100 20 100 parameter unit max. typ. min. t5 t6 t7 ns ns ns
11 mb15f02 n phase detector output waveform note: phase error detection range = - 2 p to +2 p pulses on do if/rf signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on oscin input frequency as follows. t wu > 8/fosc: i.e. t wu > 625ns when foscin = 12.8 mhz t wl < 16/fosc: i.e. t wl < 1250ns when foscin = 12.8 mhz t wu fr if/rf fp if/rf t wl ld (fc bit = high) do if/rf z l (fc bit = low) z h do if/rf if?ll section rf?ll section ld output locking state / power saving state locking state / power saving state locking state / power saving state h l l l unlocking state unlocking state unlocking state locking state / power saving state unlocking state ld output logic table
12 mb15f02 n power saving mode (intermittent mode control circuit) setting a ps if(rf) pin to low, if-pll (rf-pll) enters into power saving mode resultant current consumption can be limited to 10 m a (typ.). setting ps pin to high, power saving mode is released so that the device works normally. in addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. in general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. such case, if the pll is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an unde?ed phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. to prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. thus keeping the loop locked. allow 1 m s after frequency stabilization on power-up for exiting the power saving mode (ps: l to h) serial data can be entered during the power saving mode. during the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 m a per one pll section. at that time, the do and ld become the same state as when a loop is locking. that is, the do becomes high impedance. a vco control voltage is naturally kept at the locking voltage which de?ed by a lpfs time constant. as a result of this, vcos frequency is kept at the locking frequency. note: ps pin must be set ? at power-on. the power saving mode should be released at 1 m s after the power supply becomes stable. ps if ps rf if-pll counters rf-pll counters osc input buffer l l off off off h l on off on l h off on on h h on on on ?i1?j ?i2?j ?i3?j v cc clock data le ps on (1) ps = l (power saving mode) at power-on. (2) set serial data after power supply remains stable. (3) release saving mode (ps: l ? h) after setting serial data.
13 mb15f02 n typical characteristics (continued) x [ta = +25 c] input sensivity of fin (if) vs. input frequency main. counter div. ratio=1032 swallow=?n? rf: active fosc=19.8 mhz (?db) v? (dbm) spec spec +10 0 ?0 ?0 ?0 ?0 0 500 1000 1500 2000 ? (mhz) v? (dbm) v cc =2.7 v v cc =3.0 v v cc =3.6 v [ta = +25 c] main. counter div. ratio=4104 swallow=?n? if: active fosc=19.8 mhz (?db) 0 1000 2000 3000 ? (mhz) +10 0 ?0 ?0 ?0 ?0 v cc =2.7 v v cc =3.0 v v cc =3.6 v input sensivity of fin (rf) vs. input frequency x x x x x x x x x x x x x x x x x x x x x x
14 mb15f02 (continued) [ta = +25 c] input sensivity of osc (if) vs. input frequency ref. counter div. ratio=2048 rf: ? = 1005 mhz (vco) if: ? = 270 mhz (vco), x? = 1000 pf pull down spec +10 0 ?0 ?0 ?0 ?0 ?0 ?0 0 50 100 150 200 fosc (mhz) vosc (dbm) input sensivity of osc (rf) vs. input frequency v cc =2.7 v v cc =3.0 v v cc =3.6 v x x x x x x x x x x x [ta = +25 c] ref. counter div. ratio=2048 rf: ? = 1005 mhz (vco) if: ? = 270 mhz (vco), x? = 1000 pf pull down spec +10 0 ?0 ?0 ?0 ?0 ?0 ?0 0 50 100 150 200 fosc (mhz) vosc (dbm) v cc =2.7 v v cc =3.0 v v cc =3.6 v x x x x x x x x x x x x x
15 mb15f02 (continued) (continued) d o = 1 v d o = v cc = 1 v do output current (if) conditions: ta = +25 c v cc = 2.7, 3.0, 3.6 v v oh (v) 5.000 .5000 /div .0000 .0000 2.500/div (ma) ?5.00 3.6 v 3.0 v v cc = 2.7 v 5.000 .5000 /div .0000 .0000 2.500/div (ma) 25.00 3.6 v 3.0 v v cc = 2.7 v i oh (ma) v ol (v) i ol (ma) oscin = 12.8 mhz (+10 db) fin [if/rf] = ? (= v cc ) fin [if] = 500 mhz (?0 db) oscin, fin [rf] = ? (= v cc )
16 mb15f02 (continued) do output current (rf) conditions: ta = +25 c v cc = 2.7, 3.0, 3.6 v v oh (v) 5.000 .5000 /div .0000 .0000 2.500/div (ma) ?5.00 3.6 v 3.0 v v cc = 2.7 v 5.000 .5000 /div .0000 .0000 2.500/div (ma) 25.00 3.6 v 3.0 v v cc = 2.7 v i oh (ma) v ol (v) i ol (ma) oscin = 12.8 mhz (+10 db) fin [if/rf] = ? (= v cc ) fin [rf] = 1.2 ghz (?0 db) oscin, fin [if] = ? (= v cc ) d o = 1 v d o = v cc = 1 v
17 mb15f02 (continued) 1: 778.28 w ?24.12 w 50 mhz 2: 87.25 w ?57.03 w 200 mhz 4: 19.305 w ?38.94 w 500 mhz 3: 26.805 w ?78.48 w 2.2294 pf 400.000 000 mhz 1 2 3 4 1: 312.84 w ?27.28 w 100 mhz 2: 30.344 w ?83.38 w 400 mhz 3: 12.746 w ?1 w 800 mhz 4: 11.686 w ?0.426 w 3.2808 pf 1 200.000 000 mhz 1 2 3 4 1: 7.401 k w ?0.347 k w 3 mhz 3: 116.75 w ?.0649 k w 20 mhz 4: 083.88 w ?.5473 k w 40 mhz 2: 316.75 w ?.9348 k w 2.6817 pf 10.000 000 mhz 1 2 3 4 input impedance ? if pin ? rf pin oscin pin
18 mb15f02 n reference information 10.1378 m s pll lock up time = 440 m s (1005.000 mhz ? 1031.000 mhz, within 1khz) d mkr x : 439.90929 m s y : 25.99986 mhz 30.00300 mhz 1.000 khz/div 29.99800 mhz 10.2449 m s 1.9902449 ms pll phase noise @ within loop band = 75.5 dbc/hz ref 10db/ rbw 300 hz vbw 300 hz span 50.0 khz center 1.0180000 gh z ?0.0 dbm att 10 db d mkr x : 440.02236 m s 30.00300 mhz 1.00 khz/div 29.99800 mhz 1.9901378 ms pll reference leakage @ 200 khz offset = 71.4 dbc ref 10db/ rbw 10 khz vbw 10 khz span 1.00 mhz center 1.01800 ghz ?0.0 dbm att 10 db 2000 pf 20000 pf 330 pf 2.2 k w 15 k w typical plots measured with the test circuit are shown below. each plot shows lock up time, phase noise and reference leakage. s.g lpf vco spectrum analyzer oscin do ? test circuit fvco = 1018 mhz kv = 20 mhz/v fr = 200 khz fosc = 13 mhz lpf: sample sample a evts n/a pll lock up time = 440 m s (1031.000 mhz ? 1005.000 mhz, within 1khz) y : ?6.00006 mhz
19 mb15f02 n test circuit (prescaler input/programmable reference divider input sensitivity test) mb15f02 50 w 1 2 5 4 vcc if 0.1 m f 16 15 14 12 13 11 50 w 1000pf 1000pf p. g p. g 0.1 m f vcc rf fout oscilloscope gnd 7 3 10 6 p. g 50 w 1000pf 8 9 1000pf controller (divide ratio setting) note: ssop-16 pin
20 mb15f02 n application example vco lpf tcxo 3 v 1000 pf 0.1 m f output 1000 pf from controller data ? rf 16 15 14 13 12 11 10 9 123456 7 8 vcc rf clock le x? rf ps rf do rf 3 v 0.1 m f 1000 pf 1000 pf vco lpf output lock det. osc in ? if vcc if gnd rf gnd if ld/fout ps if do if clock, data, le: schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input). mb15f02 note: ssop-16 pin
21 mb15f02 n ordering information part number package remarks mb15f02 pfv 16 pin, plastic ssop (fpt-16p-m05) mb15f02 pv 16 pin, plastic bcc (lcc-16p-m03)
22 mb15f02 n package dimensions +0.20 C0.10 +.008 C.004 +0.10 C0.05 +.004 C.002 +0.05 C0.02 +.002 C.001 index "a" 0.10(.004) 1.25 .049 0.22 .009 0.15 .006 (.0256.0047) * (.173.004) (.252.008) nom 6.400.20 4.400.10 5.40(.213) 0.650.12 * 5.000.10(.197.004) 4.55(.179)ref details of "a" part 0 10 (stand off) 0.100.10(.004.004) (.020.008) 0.500.20 1994 fujitsu limited f16013s-2c-4 c 16 pins, plastic ssop (fpt-16p-m05) * : these dimensions do not include resin protrusion. dimensions in mm (inches) (continued)
23 mb15f02 (lcc-16p-m03) 16-pin, plastic bcc c 1996 fujitsu limited c16014s-1c-1 0.3250.10 (.013.004) 0.65(.026)typ 3.40(.134)typ "a" 0.400.10 (.016.004) 3.25(.128) 0.80(.032) typ typ 4.200.10 (.165.004) 4.550.10 (.179.004) 0.80(.032)max 0.0850.040 (.003.002) (stand off) 0.40(.016) 45? e-mark 0.05(.002) 6 9 1 14 9 14 1 6 0.400.10 (.016.004) 0.750.10 (.030.004) details of "a" part 1.55(.061)typ 1.725(.068) typ "b" 0.600.10 (.024.004) 0.600.10 (.024.004) details of "b" part dimensions in mm (inches) (mounting height)
24 mb15f02 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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